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aec q100 grade 1 compliant this product conforms to specifications per the terms of the ramtron standard warranty. the product has completed ramtrons internal qualification testing and ha s reached production status. cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 001 - 86152 rev. * a revised may 07 , 2013 fm 25l04b C automotive temp. 4kb serial 3v f - ram memory features 4k bit ferroelectric nonvolatile ram organized as 512 x 8 bits high endurance 10 trillion (10 1 3 ) read/write s nodelay? writes advanced high - reliability ferroelectric process fast serial peripheral interface - spi up to 1 0 mhz frequency direct hardware replacement for eeprom spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme hardware protection software protection low power consumption low voltage operation 3.0 - 3.6v 6 a standby current (+85c) industry standard configuration automotive temperatur e - 40 c to +125 c o qualified to aec q100 specification 8 - pin gr een/rohs soic package description the fm 25l04b is a 4 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile and performs reads and writes like a ram. it provi des reliable data retention for year s while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. t he fm 25l04b performs write operations at bus speed. no write delays are incurred. data is writt en to the m emory array immediately after each byte has been transferred to the device. the next bus cycle may commence without the need for data polling. the fm25l04b is capable of supporting 10 1 3 read/write cycles, or 10 million times more write cycles th an eeprom . these capabilities make the fm 25l04b ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. examples range from data collection, where the number of write cycles may be critical, to demanding indus trial controls where the long write time of eeprom can cause data loss. the fm 25l04b provides substantial benefits to users of serial eeprom as a hardware drop - in replacement. the fm 25l04b uses the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. device specifications are guaranteed over an automotive temperature range of - 40c to +125c . pin configuration pin name function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd supply voltage vss ground ordering information fm25l04b - g a green/rohs 8 green/rohs 8 cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 2 of 1 4 figure 1. block diagram pin descriptions pin name i/o description /cs input chip select: this active low input activates the device. when high, the device enters low - power standby mode, ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 10 mhz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. /wp input write protect: this active low pin prevents write operations to the memory array or the status register. a complete explanation of write protection is provided below. si input serial input: all data is input to the device on this pin. the p in is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet idd specifications. * si may be connected to so for a single pin data interface. so output serial output: this is the data ou tput pin. it is driven during a read and remains tri - stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so may be connected to si for a single pin data interface. vdd supply power supply ( 3.0 v to 3.6 v) vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 64 x 64 fram array 9 data i / o register 8 nonvolatile status register 3 wp cs hold sck so si
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 3 of 14 overview the fm 25l04b is a serial f - ram memory. the memory array is logically organized as 512 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm 25l04b and a s erial eeprom with the same pinout is the f - ram s superior write performance and power consumption. memory architecture when accessing the fm 25l04b , the user addresses 512 locations of 8 data bits each. these data bits are shifted serially. the addresses a re accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code, and an address. the upper address bit is included in the op - code. the complete address of 9 - bits specifies each byte address uniquely. m ost functions of the fm 25l04b either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is re ad or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be compl ete. this is explained in more detail in the interface section. users expect several obvious system benefits from the fm 25l04b due to its fast write cycle and high endurance as compared with eeprom. in addition there are less obvious benefits as well. fo r example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note t hat the fm 25l04b contains no power management circuits other than a simple internal power - on reset. it is the users responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. it is recommended that the part is not po wered down with chip enable active. serial peripheral interface C spi bus the fm 25l04b employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 10 mhz. this high - speed serial bus provides high performance serial communic ation to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm 25l04b operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm 25l04b devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. note that the clock, data - in, and data - out pins are common among all devices. the chip select and hold pins must be driven separately for each fm 25l04b device. for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the /hold pin. figure 3 shows a configuratio n that uses only three pins . protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activate d by the bus master, the fm 25l04b will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm 25l04b supports m odes 0 and 3. figure 4 shows the req uired signal relationships for m odes 0 and 3. for both modes, data is clocked into the fm 25l04b on the rising edge of sck and data is expected o n the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op - codes. these op - codes specify the commands to the device. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. i mportant: the /cs must go inactive (high) after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select.
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 4 of 1 4 figure 2. system configuration with spi port figure 3. system configuration without spi port spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 4. spi modes 0 & 3 spi microcontroller fm 25 l 04 b so si sck cs hold fm 25 l 04 b so si sck cs hold sck mosi miso ss 1 ss 2 hold 1 hold 2 mosi : master out slave in miso : master in slave out ss : slave select m i c r o c o n t r o l l e r f m 2 5 l 0 4 b s o s i s c k c s h o l d p 1 . 0 p 1 . 1 p 1 . 2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 5 of 14 data transfer all data transfers to and from the fm 25l04b occur in 8 - bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of sck. outputs are dr iven from the falling edge of sck. command structure there are six commands called op - codes that can be issued by the bus master to the fm 25l04b . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register. the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op - code commands name description op - code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 a011b write write memory data 0000 a010b wren - set write enable latch the fm 25l04b will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the stat us register and writing the memory. sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register ha s no effect. completing any write operation will automatically clear the write - enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi - write disable the wrdi command disab les all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus configuration figure 6. wrdi bus configuration hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 1 0 cs sck si so cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 6 of 1 4 rdsr - read status register the rdsr command allows the bus master to verify the contents of the status regist er. reading s tatus provides information about the current state of the write protection features. following the rdsr op - code, the fm 25l04b will return one byte w ith the contents of the status register. the status r egister is described in detail in a later section. wrsr C write status register the wrsr command allows the user to select certain write protection features b y writing a byte to the status r egister. prior to issuing a wrsr command, the /wp pin must be hi gh or inactive. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enabl e latch. figure 7. rdsr bus con figuration figure 8. wrsr bus configuration (wren not shown) status register & write protection the write protection features of the fm 25l04b are multi - tiered. taking the /wp pin to a logic low state is the hardware write protect function. all write operations are blocked when /wp is low. to write the memory with /wp high, a wren op - code must first be issued. assuming that writes are enabled us ing wren and by /wp, writes to memory are controlled by the status register . as described above, writes to the status register are performed using the wrsr command and subj ect to the /wp pin. the status r egister is organized as follows. table 2. status re gister bit 7 6 5 4 3 2 1 0 name 0 0 0 0 bp1 bp0 wel 0 bits 0 and 7 - 4 are fixed at 0 and cannot be modified. note that bit 0 ( ready in eeproms) is unnecessary as the f - ram writes in real - time and is never busy. the bp1 and bp0 control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to dir ectly write the wel bit in the s tatus r egister has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify po rtions of memory that are write - protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 180h to 1ffh (upper ?) 1 0 100h to 1ffh (upper ?) 1 1 000h to 1ffh (all) the bp1 and bp0 bits allo w software to selectively write - protect the array. these settings are only used when the /wp pin is inactive and the wren command has been issued. the following table summarizes the write protection conditions.
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 7 of 1 4 table 4. write protection wel /wp protected blocks unprotected blocks status register 0 x protected protected protected 1 0 protected protected protected 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f - ram technology. unlike spi - bus eeproms, the fm 25l04b can perform sequential writes at bus speed. no page register is needed and any numb er of sequential writes may be performed. write operation all writes to the memory array begin with a wren op - code. the next op - code is the write instruction. this op - code must include the address msb. it is followed by a single byte address value. in to tal, the 9 - bits specify the address of the first byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1ffh is reached, the counter will roll over to 000h. data is written msb first. a write operation is shown in figure 9. unlike eeproms, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (afte r the 8 th clock). the rising edge of /cs terminates a write op - code operation. asserting /wp active in the middle of a write operation will have no e ffect until the byte being written has completed. read operation after the falling edge of /cs, the bus m aster can issue a read op - code. this op - code must include the address msb. it is followed by a single byte address value. in total, the 9 - bits specify the address of the first byte of the read operation. after the op - code and address are complete, the si l ine is ignored. the bus master issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1ffh is reached, the counter will roll over to 000h. data is re ad msb first. the rising edge of /cs terminates a read op - code operation. a read operation is shown in figure 10. hold the /hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transition s of /hold must occur while sck is low, but the sck and /cs pins can toggle during a hold state. figure 9. memory write (wren not shown) figure 10. memory r ead c s s c k s i s o 0 1 2 3 4 5 6 7 0 0 h i - z 1 m s b l s b 0 1 2 3 4 6 7 a 7 0 o p - c o d e 8 - b i t a d d r e s s 0 a 0 a 3 a 4 a 5 a 6 0 1 2 3 4 5 6 7 7 d a t a i n 0 1 2 3 4 5 6 m s b l s b 7 0 0 0 a 8 a 1 a 2 5 c s s c k s i s o 0 1 2 3 4 5 6 7 0 0 h i - z 1 0 o p - c o d e 0 1 2 3 4 5 6 7 7 d a t a o u t 0 1 2 3 4 5 6 m s b l s b 7 0 1 0 0 a 8 m s b l s b 0 1 2 3 4 6 7 a 7 8 - b i t a d d r e s s a 0 a 3 a 4 a 5 a 6 a 1 a 2 5
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 8 of 14 endurance the fm25l04b devices are capable of being accessed at least 10 1 3 times, reads or writes. an f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f - ram architecture is based on an array of rows and column s. rows are defined by a8 - a3 and column addresses by a2 - a0. see block diagram (pg 2) which shows the array as 64 rows of 64 - bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in t he row is counted only once in an endurance calculation. the table below shows endurance calculations for 64 - byte repeating loop, which includes an op - code, a starting address, and a sequential 64 - byte data stream. this causes each byte to experience one e ndurance cycle through the loop. f - ram read and write endurance is virtually unlimited even at 10 mhz clock rate . table 5. time to reach endurance limit for repeating 64 - byte loop sck freq (mhz) endurance cycles/sec. endurance cyc les/year years to reach limit 10 18,660 5.88 x 10 1 1 17.0 5 9,33 0 2.94 x 10 1 1 34.0 1 1,870 5.88 x 10 1 0 170.1
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 9 of 14 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +5.0v v in voltage on any pin with respect to v ss - 1.0v to +5.0v and v in < v dd +1.0v t stg storage temperature - 55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 26 0 c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods ma y affect device reliability. dc operating conditions ( t a = - 40 c to + 125 c, v dd = 3.0 v to 3.6 v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 3.0 3.3 3.6 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 10 .0 mhz - - 0.2 2 .0 ma ma 1 i sb standby current @ + 85 c @ + 125 c - - 6 20 a a 2 i li input leakage current - 1 a 3 i lo output leakage current - 1 a 3 v ih input high voltage 0.7 5 v dd v dd + 0.3 v v il input low voltage - 0.3 0. 25 v dd v v oh output high voltage @ i oh = - 2 ma v dd C 0.8 - v v ol output low voltage @ i ol = 2 ma - 0.4 v v hys input hysteresis 0.05 v dd v 4 notes 1. sck toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v ss v in v dd and v ss v out v dd . 4. characterized but not 100% tested in production. applies only to /cs and sck pins.
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 10 of 14 ac parameters ( t a = - 40 c to + 125 c, v dd = 3.0 v to 3.6v unless otherwise specified) symbol parameter min max units notes f ck sck clock frequency 0 10 mhz t ch clock high time 40 ns 1 t cl clock low time 40 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable time 3 0 ns 2 t odv output data valid time 35 ns t oh output hold time 0 ns t d deselect time 10 0 ns t r data in rise time 50 ns 2,3 t f data in fall time 50 ns 2,3 t su data setup time 5 ns t h data hold time 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi - z 3 0 ns 2 t lz /hold high to data active 3 0 ns 2 notes 1. t ch + t cl = 1/f ck . 2. this parameter is characterized but not 100% tested. 3. rise and fall times measured between 10% and 90% of waveform. capacitance ( t a = 25 c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output c apacitance (so) - 8 pf 1 c i input c apacitance - 6 pf 1 notes 1. this parameter is characterized but not 100% tested. 2. sl ope measured at any point on v dd waveform . ac test conditions input pulse levels 10% and 90% of v dd input and output timing levels 0.5 v dd input rise and fall times 5 ns output load capacitance 30 pf power cycle timing power cycle timing ( t a = - 40 c to + 125 c, v dd = 3.0v to 3.6v unless otherwise specified ) symbol parameter min max units notes t pu v dd (min) to first access start 1 - m s t pd last access complete to v dd (min) 0 - s t v r v dd rise time 30 - s/v 1 t vf v dd fall time 2 0 - s/v 1 notes 1. sl ope measured at any point on v dd waveform . v d d m i n t p u v d d c s t v r t p d t v f
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 11 of 14 serial data bus timing /hold timing data retention ( v dd = 3.0v to 3.6v) parameter min max units notes data retention @ t a = + 5 5 c @ t a = + 10 5 c @ t a = + 125 c 17 10,000 1, 000 - - - years hours hours note: data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied: (1) 17 years at a temperature of + 55 c , (2) 10,000 hours at + 105 c, and (3) 1, 000 hours at + 125 c. cs sck si so 1 / tck tcl tch tcsh todv toh tod tcsu tsu th td tr tf cs sck so hold ths thh thz tlz ths thh typical grade 1 operating profile 0 200 400 600 800 1000 1200 1400 1600 70 75 80 85 90 95 100 105 110 115 120 125 temperature (c) hours typical grade 1 storage profile 0 5000 10000 15000 20000 25000 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 temperature (c) hours
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 12 of 14 mechanical drawing 8 - pin soic (jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxxx x = part number, p = package type, t = temp (a = automotive grade, blank = ind.) r r = rev code, lllll = lot code, z = package code ric = ramtron intl corp, yy = year, ww = work week = pb - free example: fm 2 5 l 0 4 b, green/rohs soic, automotive temperature rev. b a, lot 6 4 179 , soic year 2013, work week 07 pb - free 2 5 l 0 4 b - ga b a 6 4 179 s r ic1307 xxxxx x - pt r r lllll z ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 0 . 40 1 . 27 0 . 19 0 . 25 0 - 8 recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 13 of 14 revision history revision date summary 1.0 3/14 /2011 initial release 3.0 9/12/2011 changed to production status. 3.1 3/31 /2012 improved t pu and t vf specs. document history document title: fm2 5l04b 4k b serial 3v f - ram memory (automotive temp) document number: 001 - 8 6152 revision ecn orig. of change submission date description of change ** 3912930 gvch 02/25/2013 new spec *a 3985108 gvch 0 5 / 0 7 /2013 updated soic package marking scheme
fm25l04b - automotive temp. document number: 001 - 86152 rev. * a page 14 of 14 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go /a utomotive clocks & buffers cypress.com/go/clocks interface cypress.com/go /i nterface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/ps oc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support ramtron is a registered trad emark and nodelay? is a trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semi conductor corporation, 2011 - 2013 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress p roduct. nor does it convey or imply any license under patent or other rights. c ypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products fo r use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and s ubject to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create derivative works of, and compile the cypress source c ode and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modificati on, translation, compilation, or representation of this source code except as specified above is prohibited without the express w ritten permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this materi al, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress does no t assume any liability ar ising out of the application or use of any product or circuit described herein. cypress does not authorize its products for u se as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significan t injury to the user. the inclusion of cypress product in a life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the appl icable cypress software license agreement .

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